This invention relates to synchronization across multiple channels in a high-speed serial interface, especially in a programmable logic device. More particularly, this invention relates to synchronization of either multiple receiver channels or multiple transmit channels, especially in a programmable logic device when not all channels may be used.
Recently PLDs have begun to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) high-speed serial I/O standards—e.g., the XAUI (10 Gbps Extended Attachment Unit Interface) standard. In accordance with the XAUI standard, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic. Within each transceiver, the receiver portion typically includes a phase-locked loop (“PLL”), primarily for the purpose of enabling clock data recovery from a received high-speed serial signal. In addition, the central logic typically includes a PLL, primarily for the purpose of generating a transmit clock to be used by the transmitter portion of each of the four transceivers, and in some cases for generating a reference clock for the receiver PLLs.
In most cases, the individual receivers or transmitters in a quad are intended to be used together, for multi-channel reception or transmission of related signals. However, because of skew on the device on which the various receivers or transceivers are provided, there may be difficulties in synchronizing across the various channels. For example, in the case of reception on multiple channels under the XAUI standard, successive bytes or words of a message are sent on successive channels in a “round robin” scheme. Align characters preferably are sent substantially simultaneously on each channel. Although the multiple channels may have been aligned at the source, data converted from the serial domain back to the parallel domain on the received channels may be misaligned as a result of skew between the channels. Similarly, in the case of transmission from the parallel domain to the serial domain, it is desirable for the serial output clocks of the various channels to be aligned within one period or “unit interval (UI).” However, if different channels are ready to transmit at different times, and each channel simply begins transmitting when it is ready, the clocks can easily be misaligned by more than one UI.
While it is known to provide solutions for such synchronization problems when all receivers or transmitters are in a single quad, there may be applications in which receivers or transmitters are spread across multiple quads. It would be desirable to be able to provide synchronization across multiple channels, even across quad boundaries.